The present invention relates to an electronic component and a semiconductor device wherein a plurality of chips are connected together, a method of fabricating the same, a circuit board mounted with the same, and an electronic appliance comprising the circuit board.
Semiconductor devices are used in a variety of applications such as logic devices, memory devices, CPUs, and the like. It is commonplace to integrate two or more types of electronic circuits into one semiconductor device. To do this, however, requires redesigning of the semiconductor device with added cost. It has therefore been common practice to connect a plurality of semiconductor chips for a unit of the semiconductor device. Such a semiconductor device in the prior art is fabricated by merely connecting a plurality of bare chips mounted on a circuit board through soldering bumps prepared on anyone of the bare chips.
Accordingly, the prior art such as described above lacked ingenuity in connecting the bare chips together, or in the mounting of the semiconductor device onto a circuit board.
For instance, to connect two bare chips together a bonding pad for connecting electrodes on one of the bare chips must be prepared on the other bare chip. This required redesigning of the bare chip.
Otherwise, when the bare chips were mounted on a circuit board by directly connecting any of the bare chips to a circuit board, cracks sometimes developed at the connections due to the difference in the thermal expansion coefficients of the bare chip and the circuit board.
Accordingly, with an aim at eliminating the above-described problems of the prior art, it is an object of the present invention to provide an electronic component and a semiconductor device that are capable of reducing cost or improving reliability in the connecting of chips to each other or to a circuit board, a method of fabricating the same, a circuit board mounted with the same, and an electronic appliance comprising the circuit board.
(1) An integrated type semiconductor device of the present invention comprises a first semiconductor device having a semiconductor chip with first electrodes, a stress relieving structure provided on the semiconductor chip, a plurality of wires formed from the first electrodes, and external electrodes formed on the stress relieving structure and connected to any ones of the wires; and,
a second semiconductor device having second electrodes arranged with a different spacing pitch in comparison with the first electrodes on the first semiconductor device, the second semiconductor device being electrically connected to any ones of the wires of the first semiconductor device.
In accordance with the present invention, the first semiconductor device and the second semiconductor device are connected to form an integrated type semiconductor device. Since the first semiconductor device has a stress relieving structure, any stress placed on the external electrodes can be relieved by the stress relieving structure. In other words, while bonding of the external electrodes of the first semiconductor device onto bonding pads or the like of a circuit board could create stress due to a difference in the thermal expansion coefficient of the semiconductor chip and the circuit board, such stress is relieved by the stress relieving structure.
Additionally, in preparing electrodes for a semiconductor chip, it is generally preferable to design them in the best position for that particular chip. In this case, if the electrode positions of the semiconductor chip in the first semiconductor device differ from those of the second semiconductor device having a semiconductor chip with electrodes located at positions different from the first semiconductor chip, electrodes must be designed so that the electrode positions of both units meet together to form an integrated (united) device. However, with the present invention, semiconductor chips with unmatched electrode positions can be made into an integrated semiconductor device by arranging of the wires as necessary to convert the spacing pitch.
(2) The stress relieving structure may comprise a stress relieving layer provided on the semiconductor chip, whereas the ones of the wires connected to the external electrodes may be formed extending from the first electrodes to an area on the stress relieving layer, and the external electrodes may be formed on the ones of the wires connected to the external electrodes on the stress relieving layer.
(3) The stress relieving structure may comprise a stress relieving layer provided on the semiconductor chip and connecting portions piercing through the stress relieving layer and transmitting stress to the stress relieving layer, whereas the ones of the wires connected to the external electrodes may be formed beneath the stress relieving layer, and the external electrodes may be formed on the connecting portions.
(4) The second semiconductor device may be a bare chip consisting of a semiconductor chip having the second electrodes and external electrodes prepared on the second electrodes.
In accordance with this description, the second semiconductor device is a so-called bare chip to be connected to the first semiconductor device by means of flip chip bonding. Using a bare chip as the second semiconductor device such as described above dispenses with additional processing and therefore enables reductions in cost as well as fabrication steps.
(5) The second semiconductor device may comprise a semiconductor chip having the second electrodes, a stress relieving layer provided on the semiconductor chip, and wires formed extending from the second electrodes to an area on the stress relieving layer, and external electrodes formed on the wires on the stress relieving layer.
In accordance with this description, not only the first semiconductor device but also the second semiconductor device is enabled to relieve stress by a stress relieving layer.
(6) The second semiconductor device may comprise a semiconductor chip having the second electrodes, a stress relieving layer provided on the semiconductor chip, wires formed underneath the stress relieving layer from the second electrodes, connecting portions piercing through the stress relieving layer and transmitting stress to the stress relieving layer, and external electrodes formed on the connecting portions.
(7) The second semiconductor device may comprise wires formed from the second electrodes and external electrodes formed on the wires, whereas the external electrodes of the second semiconductor device may be electrically connected to the first semiconductor device.
(8) The wires connected to the second semiconductor device may be formed on the semiconductor chip, whereas the second semiconductor device may comprise wires formed from the second electrodes and external electrodes formed on the wires, and the stress relieving layer may be formed in a region avoiding at least a part of the ones of the wires connected to the second semiconductor device.
In accordance with this description, since the stress relieving layer is formed only in a region avoiding at least a portion of the wires, this reduces the area for forming the stress relieving layer.
(9) The ones of the wires connected to the second semiconductor device may be formed on the stress relieving layer, whereas the second semiconductor device may comprise wires formed from the second electrodes and external electrodes formed on the wires.
In accordance with this description, since the wires connected to the second semiconductor device is formed on the stress relieving layer, it can be made into any desired shape without need for redesigning of the semiconductor chip. It therefore makes it possible to configure the first semiconductor device by utilizing an existing semiconductor device, thereby avoiding cost increase.
(10) The ones of the wires connected to the second semiconductor device may be formed on the semiconductor chip, whereas the second semiconductor device may comprise wires formed from the second electrodes and external electrodes formed on the wires, and the stress relieving layer may be formed in a region avoiding at least a part of the ones of the wires connected to the second semiconductor device.
(11) The ones of the wires connected to the second semiconductor device may be formed on the stress relieving layer, whereas the second semiconductor device may comprise wires formed from the second electrodes and external electrodes formed on the wires.
(12) The integrated type semiconductor device may further comprise at least one third semiconductor device electrically connected to the first semiconductor device.
In accordance with this method, at least three semiconductor devices can be connected to form an integrated type semiconductor device.
(13) The integrated type semiconductor device may further comprise a plastic package to seal both the first and second semiconductor devices, and outer leads connected to the first electrodes of the first semiconductor device.
Such a semiconductor device is referred to as a resin sealed type device.
(14) The first semiconductor device may be equipped with a radiator attached to a side opposite to a side to which the second semiconductor device is connected.
Such a configuration provides for heat radiation of semiconductor chip of the first semiconductor device.
(15) An integrated type electronic component of the present invention comprises a first electronic component having an element chip with first electrodes, a stress relieving structure provided on the element chip, a plurality of wires formed from the first electrodes, and external electrodes formed on the stress relieving structure and connected to any ones of the wires; and,
a second electronic component having second electrodes arranged with a different spacing pitch in comparison with the first electrodes on the first electronic component, the second electronic component being electrically connected to any ones of the wires of the first electronic component.
(16) A method of making an integrated type electronic component in accordance with the present invention comprises steps of electrically connecting a second electronic component to a first electronic component having an element chip with first electrodes, a stress relieving structure provided on the element chip, a plurality of wires formed from the first electrodes, and external electrodes formed on the stress relieving structure and connected to any ones of the wires, the connection being achieved through any ones of the wires.
(17) A method of making an integrated type semiconductor device in accordance with the present invention comprises steps of electrically connecting a second semiconductor device to a first semiconductor device having a semiconductor chip with first electrodes, a stress relieving structure provided on the semiconductor chip, a plurality of wires formed from the first electrodes, and external electrodes formed on the stress relieving structure and connected to any ones of the wires, the connection being achieved through any ones of the wires.
The aforementioned integrated type semiconductor device can be fabricated in accordance with the above steps.
(18) The ones of the wires connected to the second semiconductor device may have pads and be formed on the semiconductor chip, whereas the stress relieving structure may comprise a stress relieving layer provided in a region avoiding the pads, and the second semiconductor device may possess second electrodes, wires formed from the second electrodes, and external electrodes formed on the wires; the external electrodes of the second semiconductor device may be connected to the pads of the first semiconductor device.
(19) The stress relieving structure may comprise a stress relieving layer provided on the semiconductor chip, whereas the ones of the wires connected with the second semiconductor device may have pads and be formed on the stress relieving layer, and the second semiconductor device may possess second electrodes, wires formed from the second electrodes, and external electrodes formed on the wires; the external electrodes of the second semiconductor device may be connected to the pads of the first semiconductor device.
(20) At least ones of the pads of the first semiconductor device and the external electrodes of the second semiconductor device may be made from solder having a higher melting point than that used for mounting use onto a circuit board.
The above ensures that the solder bonding the pads and the external electrodes does not remelt to break down the bonding, even at a temperature when the solder, used for mounting the integrated type semiconductor device onto the circuit board, is melted in a reflow step.
(21) The pads of the first semiconductor device and the external electrodes of the second semiconductor device may b made from metal having a higher melting point than that of solder.
In accordance with this method, the pads and bumps are bonded together between the metal on the surface of the pads and the metal on the surface of the external electrodes. Since the melting points of these metals are higher than that of solder, the metals bonding the pads and the external electrodes do not remelt to break down the bonding, even if the solder, used for mounting the integrated type semiconductor device onto the circuit board, is melted in a reflow step.
(22) Sides of ones of the pads of the first semiconductor device and the external electrodes of the second semiconductor device may be made from solder and sides of others may be made from metal having a higher melting point than that of solder.
In accordance with this method, when the solder on one of the surfaces is melted to bond the connection, the metal on the other side diffuses into the solder to raise the solder remelting temperature. This ensures that the solder bonding the pads and the external electrodes does not remelt to break down the bonding, even at a temperature when the solder, used for mounting the integrated type semiconductor device onto the circuit board, is melted in a reflow step.
(23) Between the pads of the first semiconductor device and the external electrodes of the second semiconductor device, an anisotropic conductive layer containing thermosetting adhesive may be placed, and the external electrodes of the second semiconductor device and the pads of the first semiconductor device may be bonded through the anisotropic conductive layer.
In accordance with this method, since the anisotropic conductive layer contains thermosetting adhesive, which hardens at a temperature when the solder, used for mounting the integrated type semiconductor device onto the circuit board, is melted in a reflow step, the bonding between the pads and the external electrodes is prevented from breaking down.
(24) On a circuit board of the present invention, the aforementioned integrated type semiconductor device is mounted.
(25) An electronic appliance according to the present invention comprises the aforementioned circuit board.